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Table of contents
Choose a chapter from the list below to view the PDF document for that chapter. These chapters are excerpted from PA-RISC 2.0 Architecture, by Gerry Kane, published by Prentice Hall PTR, ISBN 0-13-182734-0. Print copies of the book can be ordered at www.hp.com/hpbooks.
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Traditional RISC Characteristics of PA-RISC. PA-RISC-The Genius is in the Details. A Critical Calculus: Instruction Pathlength. Multimedia Support: The Precision Process Illustrated. Integrated CPU. Extensibility and Longevity. System Organization. |
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Non-Privileged Software-Accessible Registers. Privileged Software-Accessible Registers. Unused Registers and Bits. Data Types. Byte Ordering (Big Endian/Little Endian). |
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Physical and Absolute Addressing. Virtual Addressing. Pointers and Address Specification. Address Resolution and the TLB. Access Control. |
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Caches. Control Flow. Branching. Nullification. Instruction Execution. Instruction Pipelining. |
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Interrupt Classes. Interruption Handling. Instruction Recoverability. Masking and Nesting of Interruptions. Interruption Priorities. Return from Interruption. Interruption Descriptions. |
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Computation Instructions. Multimedia Instructions. Memory Reference Instructions. Long Immediate Instructions. Branch Instructions. System Control Instructions. Assist Instructions. Conditions and Control Flow. Additional Notes on the Instruction Set. |
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This chapter provides a description of each of the instructions (except floating-point) which are supported by the PA-RISC architecture. |
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The IEEE Standard. The Instruction Set. Coprocessor Registers. Data Registers. Data Formats. Floating-Point Status Register. Floating-Point Instruction Set. |
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This chapter provides a description of each of the instructions supported by the floating-point coprocessor. |
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Exception Registers. Interruptions and Exceptions. Saving and Restoring State. |
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Performance Monitor Instructions. Performance Monitor Interruptions. Monitor Units. |
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